Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V_T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-V_T 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400Mhz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs (others' work), the retention power of the proposed GC-eDRAM is around 80-90% lower

HEVC 2D-DCT architectures comparison for FPGA and ASIC implementations

This paper compares ASIC and FPGA implementations of two commonly used architectures for 2-dimensional discrete cosine transform (DCT), the parallel and folded architectures. The DCT has been designed for sizes 4x4, 8x8, and 16x16, and implemented on Silterra 180nm ASIC and Xilinx Kintex Ultrascale FPGA. The objective is to determine suitable low energy architectures to be used as their characteristics greatly differ in terms of cells usage, placement and routing methods on these platforms. The parallel and folded DCT architectures for all three sizes have been designed using Verilog HDL, including the basic serializer-deserializer input and output. Results show that for large size transform of 16x16, ASIC parallel architecture results in roughly 30% less energy compared to folded architecture. As for FPGAs, folded architecture results in roughly 34% less energy compared to parallel architecture. In terms of overall energy consumption between 180nm ASIC and Xilinx Ultrascale, ASIC implementation results in about 58% less energy compared to the FPGA

Gate leakage logic detection for analog CMOS circuit

In micron technology node, Igate is not a big issue to circuit designer due to its negligible value. But in deep submicron technology node, Igate is one of the major and dominant leakage components. Igate is also reacts to process variation. As this issue arise, circuit designer need to aware the impact of Igate towards their design. In addition the ability to observe the Igate level is more desirable. The variation in Igate is most sensitive to oxide thickness, TOX, due to their exponential relationship (Mukhopadhyay and Roy, 2003). It will rise by the factor of 4,000 from 90 nm to 50 nm node (Helms, Schmidt and Nebel, 2004). TOX tends to vary from one process corner to another, resulted in the variation in Igate. In digital circuit, Igate will contribute to increase off state power consumption. In contrast, for analog circuit, simple current mirror with large ratio will suffer on unexpected output current due to the leakage path from gate to ground

VLSI design of a split parallel two-dimensional HEVC transform

This paper proposes a highly parallel two-dimensional (2D) HEVC transform hardware architecture, implemented in 32-nm VLSI technology. The design allows very high-resolution and frame-rate video coding by way of a very fast HEVC transform operations. It is based on a split architecture, where the individual transform type and size is separated into its own core, therefore enables pixel-level parallelism in the 2D parallel and folded structures. This work also implements the full specification of the HEVC transform for both the DCT and DST transforms, with performance, power, and area analyses for the two structures. Results show very significant speed up over existing unified architectures, with only a relatively modest increase in total gate count. The design is suitable for applications that require very high video resolution and frame rate

Comprehensive analysis of gate oxide short in junctionless fin field effect transistor

Junctionless (JL) FinFET is one of the most promising alternatives to FinFET and planar MOSFET for future performance enhancements. The complexity of the JL FinFET manufacturing process has prompted difficulties in reliable device testing. Gate oxide short (GOS) is one of the most common faults that substantially influence circuit reliability, specifically in FinFET device structure. In this work, GOS defect model is presented for both n-channel and p-channel JL FinFET and JL FinFET-based inverter by introducing the defect as a pinhole designated by small cuboid cuts of different sizes for several coordination in the dielectric and filled with gate material. The electrical characteristics of 15nm n- and p-channel JL FinFET with fin height and width of 10nm, source/drain, channel and substrate doping concentration of 1.5×1019 cm-3, and work function of 4.76eV and 4.52eV for n- and p-channel are successfully simulated by using Synopsys Sentaurus TCAD Tools where Vth, SS, and DIBL are 0.371V, 75.7mV/dec and 42.7mV for n-channel and 0.3298V, 79.1mV/dec and 48.9mV for p-channel JL FinFET respectively that is compared with post GOS defect injection. The high-to-low delay time (tHL) is 1.61ps and low-to-high delay time (tLH) is 1.74ps for the defect-free inverter that is compared to the defected one where the tHL is 16.1 % and tLH is 22.4 % smaller than defective inverter. The findings of this research potentially result in the formation of a realistic analytical GOS fault model for circuit-level modeling

The design of built in current extractor circuit for IDDQ test

Control, mechatronics & automation, Vision, image & signal processing, Artificial intelligence & computer applications, Electronic design & applications, Telecommunication systems & applications, etc

Digital detection of gate leakage for analog CMOS circuit

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